The present disclosure relates generally to circuit boards, and more particularly, to a circuit board configured to provide multiple interfaces.
FIG. 1 is a block diagram illustrating a conventional mother board using a low voltage transistor logic (LVTTL) interface. Typically, the mother board using an LVTTL interface comprises a bus 1 having one end connected to a chip set 2 and other end connected to a plurality of memory slots 3 inserted with DRAM modules 4. Here, the chip set 2 is a controller used in a board for LVTTL.
FIG. 2 is a block diagram illustrating a conventional mother board using a series stub terminated transceiver logic (SSTL) interface. The mother board using an SSTL interface comprises a bus 5 having both ends connected to the termination resistances 6. The termination voltages VTT are applied to the termination resistances 6. One end of the bus 5 is connected to a chip set 7, and the other end of the bus 5 is connected to a plurality of memory slots 8 inserted with DRAM modules 9. The chip set 7 is a controller used in a board for SSTL. Here, the termination resistances 6 used in the mother board prevent noise caused by echo to improve high operation. However, there is a problem because current consumption is increased during the operation.
In general, an LVTTL interface is used when SDRAM operates at relatively low speed while an SSTL interface is used when DDR SDRAM operates at relatively high speed. Typically, mother boards are used for SSTL interfaces but not for LVTTL interfaces because the termination resistances 6 are directly formed on the board. That is, if DDR SDRAM using an SSTL interface as DRAM module needs to use an LVTTL interface, the mother board of DDR SDRAM should be substituted with a mother board providing an LVTTL interface.
A circuit board configured to provide multiple interfaces by selectively inserting a module formed of termination resistance into a slot is disclosed herein. Further, the board may be configured to provide multiple interfaces by selectively connecting termination resistance.
In particular, the board comprises: a bus configured to transmit data; a chip set connected to one end of the bus and configured to change setting of a memory driven system according to a logic; a plurality of memory slots connected to the other end of the bus, each memory slot configured to receive a memory module; and a plurality of termination slots correspondingly connected to each end of the bus, each termination slot configured to receive a termination module applying a termination voltage.
Alternatively, the board comprises: a bus configured to transmit data; an ordinary chip set connected to one end of the bus and configured to change for setting of a memory driven system according to a logic; a plurality of memory slots connected to other end of the bus, each memory slot configured to receive a memory module; a plurality of termination resistances correspondingly connected to each end of the bus, each termination resistance configured to apply a termination voltage; and a plurality of switching circuits connected between the bus and each termination resistance. Each of the plurality of switching circuits is configured to selectively connect the bus and each termination resistance according to the logic.